A novel arithmetic reformulation that dramatically accelerates large-scale SPICE simulations. Verified against industry-standard reference circuits.
As analog circuits scale in complexity, traditional SPICE solvers face a quadratic explosion in compute time. Monte Carlo yield analysis for advanced process nodes can take weeks or months, stalling tape-out schedules and inflating R&D costs.
Large-scale Monte Carlo simulations with 10,000+ iterations on complex analog blocks consume enormous HPC resources and calendar time.
Cloud and on-premise compute costs for exhaustive yield analysis on advanced nodes are growing faster than Moore's Law can offset.
Every additional week of simulation delay pushes back the tape-out window, potentially missing critical MPW shuttle deadlines.
All benchmarks measured against well-known reference circuits using industry-standard SPICE solvers. Results independently reproducible under MNDA.
1,024-node distributed RC network · Transient sweep 0–10μs
Analog block · 10,000 Monte Carlo iterations · Process variation ±3σ
Sub-1V bandgap · AC sweep 1Hz–10GHz · 1,000 frequency points
4,096 × 4,096 conductance matrix · LU decomposition equivalent
All benchmarks conducted on identical hardware (AMD EPYC 7763, 256GB DDR4). Numerical accuracy verified within 0.3% of the industry-standard NGSPICE 46 solver output across all test circuits. Detailed methodology available under Mutual NDA.
Analog verification typically consumes 30–40% of total pre-silicon R&D spend and is the single largest driver of schedule delays. Here is the projected impact of Sibacus-SPICE on a typical advanced-node tape-out program.
Typical Monte Carlo yield verification campaigns requiring $500K–$2M in cloud HPC spend can be completed for a fraction of the cost.
Verification phases that typically consume 8–14 weeks of calendar time can be compressed to days, keeping MPW shuttle deadlines on track.
Design engineers spend less time waiting for simulation results and more time iterating on circuit performance, dramatically improving team productivity.
Non-Recurring Engineering costs for new process node bring-up are slashed by enabling more design iterations within the same budget window.
Estimates based on published industry data for analog/mixed-signal verification at 22nm–7nm nodes. Actual savings depend on circuit complexity, iteration count, and existing infrastructure. Detailed ROI projections available upon request.
Sibacus-SPICE introduces a fundamentally new approach to the core numerical engine powering analog circuit simulation.
A proprietary reformulation of the numerical solver engine that eliminates the dominant computational bottleneck in traditional SPICE matrix operations.
Accepts standard SPICE netlists and process models (e.g., BSIM). No changes to existing design flows, PDKs, or verification methodologies required.
Dynamically adjusts numerical precision per simulation region, concentrating computational resources where they matter most for accuracy.
Architected for embarrassingly parallel Monte Carlo workloads, scaling linearly across cloud HPC clusters and on-premise compute farms.
Benchmarked against industry-standard SPICE solvers on well-known reference circuits. Numerical fidelity within 0.3% across all test vectors.
The arithmetic core is designed for direct mapping onto FPGA and ASIC substrates, enabling future dedicated simulation hardware appliances.
Accelerate the exhaustive simulation campaigns required to characterize new process nodes and build production-quality Process Design Kits.
Run 10,000+ iteration Monte Carlo simulations in minutes instead of days, enabling true statistical yield optimization before tape-out.
De-risk next-generation process nodes by running full-array simulations that were previously computationally infeasible.
Accelerate the massive simulation campaigns required to qualify SRAM bitcells, compilers, and macros across process nodes and operating conditions.
Sibacus-SPICE is currently available to select foundry and design partners under Mutual NDA. Contact us to schedule a technical demonstration and review benchmark methodology.