Research

Open problems and active investigations in BSA-CIM

BSA-CIM is early in its development curve — proven physics, first-generation architecture, enormous headroom. These are the research vectors we are actively pursuing. Each represents a real improvement opportunity grounded in device physics and circuit-level engineering.

RRAM Device Engineering
Materials / Endurance / Reliability

Binary RRAM cells achieve 10⁴–10⁶ write cycles today. For on-device training where weights are updated in-field, higher endurance is needed.

  • → New oxide stacks and interface engineering targeting 10⁸+ cycles
  • → Forming-free RRAM processes to simplify manufacturing
  • → Retention vs. endurance trade-off characterization across temperature
3D RRAM Stacking
Vertical Density Scaling

Because RRAM is BEOL, multiple memory layers can be stacked vertically — a density scaling axis unavailable to SRAM or DRAM architectures.

  • → Multi-layer crosspoint array process integration
  • → Inter-layer via routing to peripheral circuits (ADCs, BSA logic)
  • → Cross-layer uniformity characterization for binary cells
On-Device Training
Restricted Updates / Continual Learning

Restricted-update training achieves 98% accuracy recovery at 12-layer scope. Extending this to deeper models and more update patterns is an active research area.

  • → Depth-scaled update rates (different learning rates per layer depth)
  • → Curriculum scheduling for write-endurance budgeting
  • → Federated narrow-model training across edge devices
ADC / Peripheral Co-design
Circuit-Level Energy Optimization

The ADC is the largest peripheral energy consumer in any CIM architecture. CSD encoding naturally reduces the number of conversions required — but there's more to extract.

  • → SAR/sigma-delta ADC co-optimization with sparse CSD outputs
  • → Dynamic ADC resolution scaling based on layer sensitivity
  • → Sense amplifier sharing across multi-bank arrays
CSD Encoding Co-training
Model-Architecture Co-optimization

Current CSD encoding achieves R̄ = 2.27 binary cells per weight on post-trained models. Training with CSD constraints from initialization could push sparsity further.

  • → CSD-aware weight regularization during training
  • → Target R̄ < 2.0 — fewer cells per weight means more capacity per die
  • → Architecture search over CIM-friendly topologies (e.g., structured sparsity)
Dynamic-R Runtime
Adaptive Precision at Inference

Today, the number of BSA recurrences (R) is fixed per layer. Adapting R at runtime based on token importance or attention head sensitivity is an unexplored frontier.

  • → Per-token adaptive precision (skip recurrences for confident predictions)
  • → Per-head R allocation in attention layers
  • → Energy-accuracy Pareto characterization across model families

Pre-silicon, by design. We are openly sharing our research directions because the physics is the moat, not secrecy. These are real engineering problems with tractable solutions — each one represents a meaningful improvement to the BSA-CIM platform that doesn't require a new transistor node.

If you are a researcher, university lab, or engineering team working on RRAM devices, CIM architectures, or edge ML systems, we welcome collaboration. Reach out at research@sibacus.me.