BSA-CIM Architecture
Breaking the Thermodynamic Wall through Binary-Cell In-Memory Compute
For decades, Dennard scaling — the principle that as transistors shrink, their power consumption drops proportionally — allowed each new chip generation to compute more while using less energy. That era is over. Below 7nm, transistor switching energy has flatlined; shrinking the transistor no longer reduces its power cost. Moore's Law still delivers more transistors per die, but without the power dividend. The only remaining lever to reduce the thermodynamic cost of computing is to eliminate the physical movement of data. The Sibacus architecture is built on this singular insight.
This is why the opening exists. The industry is pouring its capital into the exhausted lever. Terafab — the Tesla / SpaceX / xAI / Intel venture on Intel's 18A leading-edge node — commits $20–25 billion initially, rising to a SpaceX-estimated $119 billion across all phases, to advance leading-edge AI silicon one more generation. But with Dennard scaling ended, that shrink barely lowers energy for the memory-bound inference that now dominates AI — and the scale of capital required is itself the signature of diminishing returns. The architectural lever — eliminating data movement — is orthogonal to the node, targets multiples on that dominant workload (modeled 4–8× system-level, weight-bound inference), and remains uncontested by the very players spending the most. The most valuable move in silicon is no longer the smallest transistor; it is the shortest distance between memory and compute.
1. The Thermodynamic Wall: The Memory Bottleneck
Why standard CPU and GPU architectures are structurally inefficient.
In standard von Neumann processors, neural network weights are stored in off-chip memory (DRAM/HBM) and must be shuttled over copper wires to the arithmetic logic units (ALUs) for every single computation. This separation between storage and logic — the memory wall — is the dominant source of energy waste in modern AI hardware.
With transistor switching energy effectively plateaued below 7nm, the logic gates themselves are no longer the bottleneck. The physics is clear:
- DRAM Memory Access Cost: ~20 pJ / bit (Horowitz, ISSCC 2014)
- Logic ALU Multiply Cost: ~0.01 pJ / op (at 7nm)
Data movement costs hundreds to thousands of times more than the arithmetic it feeds — a gap that holds at every process node, because off-chip transfer energy is set by driving the bus, not by the transistor. Physics has closed every other optimization door — the only remaining lever is to stop moving data entirely.
(Weights)
(Compute)
2. The Solution: Compute-in-Memory with RRAM
Moving the compute to where the data already lives.
If the problem is data movement, the solution is to move the compute to where the data already lives. Resistive RAM (RRAM) makes this physically possible for a specific reason: its programmable conductance directly represents a neural network weight. Unlike SRAM, RRAM is non-volatile (zero standby power, no refresh cycles), and its dense crossbar geometry naturally maps to the matrix multiply that dominates neural network inference.
By applying voltages to an RRAM crossbar array, we perform matrix arithmetic in-place — weights never leave their physical storage location:
- Ohm's Law (I = V × G): Input activations are applied as voltage vectors (V). Current flowing through programmed memory cells represents multiplication, where conductance (G) represents the weight.
- Kirchhoff's Current Law (Itotal = ∑ Ii): Current vectors sum along the columns in parallel, performing dot-product accumulation in a single cycle.
3. The Multi-Level Cell (MLC) RRAM Problem
Why typical analog memory computing is commercially problematic.
Many analog CIM designs attempt to encode multi-bit weight values (e.g. 3-bit or 4-bit numbers) using multi-level resistance states within a single RRAM cell. However, intermediate conductance states are highly unstable. Due to thermal fluctuations and ionic migration, these levels suffer from severe write dispersion and conductance drift (decaying up to 10-15% over time), degrading neural network accuracy and requiring power-hungry, continuous digital calibration loops.
4. The Sibacus Solution: Binary-Cell + BSA Logic
Ensuring drift-free stability with 100% binary storage.
To bypass analog drift completely, Sibacus maps weights onto binary-cell (1-bit) storage inside the RRAM. A cell is programmed to either a fully Low-Resistance State (LRS) or High-Resistance State (HRS). This yields drift immunity by construction — and because it needs only two resistance states, it is a substantially simpler qualification target than multi-level cells, aligning with the binary eNVM integration flows foundries are already building toward.
Multi-bit weights are represented by decomposing values using sparse Canonical Signed Digit (CSD) formatting:
W ≈ ∑r=1..R sr · 2er, sr ∈ {+1, -1}
These terms are processed bit-serially using compact Bit-Serial Addition (BSA) shift-and-add logic adjacent to the RRAM column outputs.
5. Physical ASIC Synthesis & Model Benchmarks
Measured numbers from standard-cell sky130 flows and real trained LLM workloads.
Model Accuracy & Sparsity
On the fully trained SmolLM2-135M model, a lossless CSD conversion yields an average of R̄ = 2.273 active terms across the entire 134.5M weight parameter distribution.
This result is not model-specific. Cross-family validation on Meta NLLB-600M (a translation model with fundamentally different weight structure) yields R̄ ≈ 2.3–2.4 — closely tracking SmolLM2. Noise budget Monte Carlo confirms CSD beats dense binary at every device-noise corner for both families (3.6–11.2% RMS for NLLB vs. 3.8–11.4% for SmolLM2).
PE Gate-Level Truth
Standard-cell synthesis (sky130) proves that at the individual gate-level, the BSA PE has no dynamic energy advantage over a conventional INT8 MAC (parity at best, and 1.5× area footprint). However, by implementing Dynamic-R term gating (disabling inactive slices), activity scales down linearly. When average active terms R̄ are kept ≤ 1.6, the BSA PE achieves dynamic switching parity with the MAC.
Key Insight
The energy optimization and the accuracy optimization are the same physical mechanism: sparse CSD term-planes mean fewer ADC conversions (lower energy) and concentrate ADC resolution onto smaller summed ranges (higher effective precision). This is measured, not modeled.
| Active Terms (R) | Distribution Share |
|---|---|
| R=0 (Fully Sparse) | 1.4% |
| R=1 | 14.7% |
| R=2 (Analog CIM) | 43.6% |
| R=3 (Digital co-PE) | 35.7% |
| R=4 (Digital co-PE) | 4.5% |
| Weighted Average (R̄) | 2.273 |
While gate-level ALU energy is roughly at parity, the system-level win is structural: by computing inside memory, weights are never fetched from DRAM. For weight-dominated, batch-1 edge workloads — the flagship target — this bypasses the 20 pJ/bit transfer wall entirely, delivering 4–8× system-level energy efficiency vs. GPU references and up to ~20× for single-stream serving (where GPUs pay the full HBM weight fetch every token).
Boundary: with conventional full-attention models, both architectures become KV-cache bound at long context (8K+ tokens) and the advantage narrows toward parity. Hybrid-SSM/MLA models served under sparse attention restore a context-independent advantage in our energy model [modeled]; regardless, the flagship claim rests on the weight-dominated, batch-1 edge case where the win is largest — not a blanket claim.
6. Why CIM's Improvement Curve Is Just Beginning
Conventional scaling optimizes the wrong 5%. CIM optimizes the dominant 95%.
Conventional Path: Diminishing Returns
The semiconductor industry is spending hundreds of billions to shrink transistors from 3nm → 2nm → 1.4nm. But since Dennard scaling ended:
- ✕ Smaller transistors no longer reduce power — they pack more into the same thermal envelope, generating more heat per mm²
- ✕ Quantum effects worsen — tunneling leakage increases below 3nm, requiring complex gate-all-around (GAA) structures
- ✕ Costs escalate exponentially — EUV lithography tools cost $300M+ each; a 2nm fab exceeds $25B
- ✕ Yields drop — fewer functional dies per wafer at every new node
- ✕ The memory wall is untouched — a 1.4nm transistor still fetches weights from DRAM at 20 pJ/bit. The wire didn't shrink.
Exponentially more capital for linearly diminishing returns — on the 5% of energy that goes to compute, while ignoring the 95% that goes to data movement.
CIM Path: Early Curve, Right Problem
RRAM Compute-in-Memory is where CMOS was in the 1980s — proven physics, early commercial maturity, enormous headroom. Improvement vectors that haven't been fully exploited:
- → RRAM device endurance — binary cells at 10⁴–10⁶ cycles today; materials research (new oxides, interface engineering) targets 10⁸+
- → ADC efficiency — the largest peripheral energy cost in CIM; sparse CSD encoding reduces conversions, with more co-design gains ahead
- → Crossbar density — larger arrays mean more compute per read cycle and better energy amortization
- → 3D RRAM stacking — because RRAM is BEOL, multiple memory layers can stack vertically without shrinking the transistor. Unique to this technology class.
- → On-device training — restricted-update training at 98% recovery on edge-scale models today (measured, SmolLM2-135M); recovery is scale-dependent, and depth-scaled updates and curriculum scheduling are identified research paths for larger models
- → CSD encoding co-training — training models with CSD constraints from initialization could push sparsity below R̄ = 2.0
Modest R&D investment for large returns — on the 95% of energy that actually dominates the cost.
Vertical Scaling: 3D RRAM Stacking
Each RRAM cell is a thin metal-oxide-metal film (~20-50nm thick) deposited between metal interconnect layers at low temperatures (~300-400°C). This means additional RRAM layers can be stacked vertically without damaging the transistors or existing layers below.
SRAM requires 6 transistors per bit in the front-end silicon — it can't stack. DRAM requires deep trench capacitors in the substrate — it can't easily stack. RRAM can, because the switching element is a thin film between wires. This gives CIM a second scaling axis that is completely independent of node shrinking:
- 1. Horizontal: move to denser transistor nodes (40nm → 22nm → 14nm)
- 2. Vertical: stack RRAM layers (1 → 2 → 4 → 8)
Both are independent. You can pursue one, the other, or both simultaneously. Neither requires EUV lithography.
| Layers | Density | ~Capacity (120mm²) |
|---|---|---|
| 1 layer | 1× | ~135M params |
| 2 layers | 2× | ~270M |
| 4 layers | 4× | ~540M |
| 8 layers | 8× | ~1B+ |
Binary cells (ON/OFF) have the widest process margin of any RRAM type — the easiest to manufacture reliably across multiple stacked layers. Multi-layer RRAM has been demonstrated in research (2-4 layers); production qualification is a 3-5 year R&D horizon.
The Design Philosophy: Narrow AI at the Edge
The data center scaling race assumes that bigger models are always better — 70B, 400B, 1T parameters. This assumption only holds when all compute is centralized and all data flows to one place. At the edge, the opposite is true.
A drone inspecting power lines doesn't need a 70B general-purpose model. It needs a focused 135M model trained specifically for insulator crack detection, running at 100mW, adapting to local weather and lighting conditions with each flight. A fishing vessel doesn't need GPT. It needs a domain-specific ocean current and species model that learns from its own catch data.
This is narrow AI — smaller models that are deeply specialized and continuously learning in their operating environment. CIM is purpose-built for this paradigm:
135M-600M parameter models fit entirely in on-chip RRAM — even single-layer. No external memory needed. Zero standby power.
At 0.120 pJ/op, a focused edge model runs inference continuously on milliwatts — within the thermal budget of any form factor.
Restricted updates directly on the RRAM array let the model specialize to its environment without cloud connectivity or centralized retraining.
3D stacking provides headroom for model growth as applications demand it — but the philosophy is clear: you don't need massive models when the model is purpose-built for its domain and continuously improving where it operates.
The asymmetry is structural. Conventional scaling invests exponentially more capital for linearly diminishing returns on the wrong bottleneck. CIM addresses the dominant energy cost — data movement — and its improvement curve hasn't flattened yet. Being early on the right curve is better than being late on the wrong one.