Architecture Roadmap & Futures Analysis
Execution milestones, strategic threat mitigation, and comparative physics for Sibacus silicon.
Sibacus is built on proven physics, validated emulation platforms, and a clear fabrication roadmap. Below, we outline our multi-horizon development milestones followed by a transparent Technology Futures & Risk Analysis—examining competing paradigms like Silicon Photonics, SRAM-CIM, and 1-Bit AI models to define Sibacus's long-term physical moat at the edge.
Horizon 1: Emulation & First-Gen Tape-Out
Milestones: 12–18 Months | Validating physical silicon and compiler parity.
Instead of quantizing post-training, we train model weights with Canonical Signed Digit (CSD) constraints from the start. This pushes sparsity down to target R̄ < 2.0, reducing active cells per weight and maximizing array density.
The Analog-to-Digital Converter is the primary peripheral energy consumer in CIM. We implement SAR and sigma-delta ADC structures co-optimized with sparse CSD activations to eliminate peripheral power taxes.
Verifying our Dual-Engine Co-Mapping (Analog CIM RRAM crossbars + Digital co-PE) on high-speed hardware emulation platforms, testing SmolLM2 and NLLB model outputs against standard CPU/GPU execution.
Horizon 2: On-Device Specialization
Milestones: 18–36 Months | Continuous local adaptation and runtime optimizations.
Implementing restricted-update binary weight modifications directly on the RRAM array. This enables models to adapt to local sensor feedback loops in-field, without requiring heavy digital backpropagation or cloud connectivity.
Implementing runtime precision scaling. The engine dynamically skips Bit-Serial Addition (BSA) recurrence slices for high-confidence tokens or insensitive layer depths, scaling active compute power down on the fly.
Developing curriculum learning and write-endurance scheduling algorithms. By distributing updates across the RRAM array, we maximize cell lifetime (targeting 10⁶+ write cycles).
Horizon 3: 3D Stacking & Frontier Scale
Milestones: 36–60+ Months | Vertical density × chiplet composition × sparse activation to support frontier models.
Integrating multiple layers of binary RRAM vertically in the Back-End-of-Line (BEOL). Stacking layers scales density to the tens-of-billions parameter class per die on mature, low-cost nodes—bounded by thermal budget, not transistor pitch.
Aligning binary-cell RRAM crossbar geometries with standard foundry embedded non-volatile memory (eNVM) process flows. This enables clean, multi-source IP licensing across major global fabs.
Orchestrating cooperative, low-power inference across many unplugged local devices—each an independent narrow specialist that shares context and partitions model state without central coordination. Where the cloud runs a Mixture of Experts inside one model, the edge fields an Army of Experts across the physical world.
Cloud — Mixture of Experts: one model, a gating router activates a few expert sub-networks per token. Composed via 3D stacking (per-die density) then chiplets on a 2.5D/3D interposer—the same packaging that scales HBM—for trillion-parameter capacity. Non-volatility makes sparse routing an energy win: provision a trillion parameters, pay only for the experts each token wakes.
Edge — Army of Experts: many independent narrow models, each a complete specialist on its own device, federating across the physical world. The "router" is physical deployment; sparse activation is spatial. An idle sensor's whole model draws zero power until its moment—the same non-volatile dormancy, distributed.
Technology Futures & Threat Mitigation
An objective evaluation of alternative compute paradigms—from Silicon Photonics to 1-Bit AI models—and how Sibacus secures its physical moat at the edge and in orbit.
Paradigm Comparison: GPUs vs. Photonics vs. Sibacus BSA-CIM
Evaluating architectural trade-offs across physics, energy, and edge viability.
| Architecture Paradigm | Primary Vector / Medium | Data Commute Overhead | Standby Leakage & Thermal | Edge & Orbital Viability |
|---|---|---|---|---|
| Centralized Cloud GPUs | Copper Wires (Von Neumann) | Severe (~20 pJ/bit DRAM transfer) | High leakage; requires GW grids & liquid cooling | Unviable (700W per chip) |
| Silicon Photonics (Optical) | Lasers / Waveguides (Photons) | High ADC/DAC Conversion Tax | Requires active micro-heaters for laser tuning | Ideal for rack interconnects; poor for on-chip RAM |
| Sibacus BSA-CIM (RRAM) | 22nm BEOL 1T1R Cell Arrays | Zero Commute (0.239 pJ/MAC) | Zero Standby Power; 100% Passive Cooling | Native Home Turf (Sub-watt to 1W) |
Threat 1: Silicon Photonics & Optical Computing
Risk Horizon: 3–5 Years | Impact: Medium
The Threat: Co-packaged optical interconnects (e.g. Celestial AI, Ayar Labs) use lasers to shuttle data between DRAM and compute chiplets with low attenuation, attempting to bypass copper wire losses.
The Physical Bottleneck: Light cannot be statically stored (no "optical RAM"). Photonic computing requires continuous Analog-to-Digital (ADC) and Electro-Optical conversions, while thermal drift requires active heaters that burn electrical watts.
Threat 2: Digital SRAM-CIM on 3nm/2nm GAA Nodes
Risk Horizon: 3–5 Years | Impact: High
The Threat: Embedding digital accumulators in standard SRAM arrays on 3nm/2nm Gate-All-Around (GAA) PDKs to deliver high SRAM compute density without custom BEOL materials.
The Physical Bottleneck: SRAM is volatile and suffers from continuous standby leakage power. At 3nm, SRAM cell area scaling has flatlined (~0.021 μm²), making large model storage prohibitively expensive per die.
Trend 3: 1-Bit & Ternary Quantization (BitNet)
Risk Horizon: 1–3 Years | Opportunity: Very High
The Shift: Algorithmic breakthroughs like BitNet b1.58 replace floating-point multiplications with ternary weights ({-1, 0, 1}), dramatically simplifying matrix math.
The Strategic Alignment: Rather than threatening Sibacus, 1-bit models match Sibacus's Canonical Signed Digit (CSD) binary 1T1R crossbar structure perfectly.
Pillar 4: Foundry Multi-Sourcing & Software Parity
Execution Strategy: Ongoing | Moat Defense
Foundry Multi-Sourcing: Mitigating 22nm BEOL RRAM supply chain risks by qualifying IP across both GlobalFoundries (22FDX) and TSMC (22ULL) PDKs simultaneously.
1-Click Developer Compiler Stack: Maintaining seamless ONNX / TVM runtime compilation so developers can deploy PyTorch models to Sibacus silicon without touching low-level assembly.
"While hyperscalers build megawatt furnaces in desert data centers, Sibacus holds the physical key to intelligence where the world actually happens—on the edge, in the air, and in orbit."
Pre-Silicon, by Design.
We openly publish our technical roadmap and futures analysis because the architecture and the physics of the binary-cell RRAM implementation are the moat. If you are a university lab, foundry partner, or system engineer working on in-memory compute, we welcome collaboration at research@sibacus.com.